The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to flash memory cells having trench source-line connections and their operation.
Electronic information handling or computer systems, whether large machines, microcomputers or small and simple digital processing devices, require memory for storing data and program instructions. Various memory systems have been developed over the years to address the evolving needs of information handling systems. One such memory system includes semiconductor memory devices.
Semiconductor memory devices are rapidly-accessible memory devices. In a semiconductor memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells.
Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of semiconductor memory device includes a non-volatile memory made up of floating-gate memory cells called flash memory. Flash memory is often used where regular access to the data stored in the memory device is desired, but where such data is seldom changed. Computer applications use flash memory to store BIOS firmware. Peripheral devices such as printers store fonts and forms on flash memory. Digital cellular and wireless applications consume large quantities of flash memory and are continually pushing for lower voltages and higher densities. Portable applications such as digital cameras, audio recorders, personal digital assistants (PDAs) and test equipment also use flash memory as a medium to store data.
Conventional flash memory cells make use of a floating-gate transistor. In such devices, access operations are carried out by applying biases to the source, drain and control gate of the transistor. Write operations are generally carried out by channel hot-carrier injection. This process induces a flow of electrons between the source and the drain, and accelerates them toward a floating gate in response to a positive bias applied to the control gate. Read operations generally include sensing a current between the source and the drain, i.e., the MOSFET current, in response to a bias applied to the control gate. Erase operations are generally carried out through Fowler-Nordheim tunneling. This process may include electrically floating the drain, grounding the source, and applying a high negative voltage to the control gate.
Designers are under constant pressure to increase the density of flash memory devices. Increasing the density of a flash memory device entails fabricating greater numbers of memory cells in the same area, or real estate, of an integrated circuit die. To do so generally requires closer packing of individual memory cells, thus reducing spacing between memory cells. It is becoming increasingly difficult to further reduce spacing between memory cells. Closer packing also generally requires smaller dimensions of device elements. Smaller dimensions of many device elements, such as conductive traces or lines, leads to increased resistance. This increased resistance detrimentally impacts the speed and power requirements of the memory device.
One approach commonly used to reduce resistance from the source regions of the memory cells is to couple multiple source regions of adjacent rows into a source line. Each source line generally extends for several columns, e.g., 16 columns. These source lines are then coupled to a low-resistance strap, often a metal line in the metal-1 layer of the integrated circuit fabrication process. As the resistance of the source lines increases due to reducing line widths, it is generally necessary to reduce the spacing of these low-resistance straps to manage resistance levels to the memory cells located farthest from the straps. This results in increasing numbers of metal lines and counterproductive use of semiconductor die area.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate architectures for arrays of floating-gate memory cells, apparatus making use of such memory arrays, and methods of their fabrication and operation.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
As packing of floating-gate memory cells becomes more dense, resistance levels of source-line connections become more difficult to manage. Floating-gate memory cells of the various embodiments are formed in a first semiconductor region having a first conductivity type. This first semiconductor region is separated from the underlying substrate by an interposing second semiconductor region having a second conductivity type different from the first conductivity type. The source regions of the memory cells are coupled to the second semiconductor region as a common source line. In this manner, source-line resistance is improved without the need for metal lines or other low-resistance straps placed at regular intervals across the memory array, thus permitting tighter packing of memory cells.
For one embodiment, the invention provides a floating-gate memory cell. The memory cell includes a gate stack having a control-gate layer and having a floating-gate layer interposed between the control-gate layer and a first semiconductor region having a first conductivity type. The memory cell further includes a drain region in the first semiconductor region and a source region in the first semiconductor region. The drain region and the source region have a second conductivity type different from the first conductivity type. The source region is coupled to a second semiconductor region underlying the first semiconductor region, wherein the second semiconductor region has the second conductivity type.
For another embodiment, the invention provides a floating-gate memory cell. The memory cell includes a tunnel dielectric layer overlying an upper well region, wherein the upper well region has a p-type conductivity. The memory cell further includes a floating-gate layer overlying the tunnel dielectric layer, an intergate dielectric layer overlying the floating-gate layer, a control-gate layer overlying the intergate dielectric layer, a drain region in the upper well region, and a source region in the upper well region. The drain region and the source region each have an n-type conductivity. The source region is coupled to a lower well region underlying the upper well region and having an n-type conductivity. The lower well region is formed in a semiconductor substrate having the p-type conductivity.
For yet another embodiment, the invention provides a memory device. The memory device includes a substrate having a first conductivity type, a lower well region formed in the substrate, and an upper well region formed in the lower well region. The upper well region has the first conductivity type and the lower well region has a second conductivity type different from the first conductivity type. The memory device further includes a plurality of word lines, a plurality of bit lines, and a plurality of floating-gate memory cells. Each floating-gate memory cell includes a control-gate layer for coupling to one of the plurality of word lines, a floating-gate layer interposed between the control-gate layer and the upper well region, a drain region in the upper well region for coupling to one of the plurality of bit lines, a source region in the upper well region, and a source-line contact extending below the source region to the lower well region. The drain region and the source region each have the second conductivity type. The source-line contact couples the source region to the lower well region either directly, e.g., extending through the source region, or indirectly, e.g., laterally displaced yet in electrical contact with the source region.
For still another embodiment, the invention provides a method of erasing a floating-gate memory cell. The method includes applying a first potential to a control gate of the floating-gate memory cell. The floating-gate memory cell has a drain region and a source region formed in a first well region having a first conductivity type. The first well region is formed in a second well region having a second conductivity type different from the first conductivity type. The method further includes applying a second potential to the first well region and the second well region. The second potential is higher than the first potential and the second well region is coupled to the source region.
For a further embodiment, the invention provides a method of forming a memory cell. The method includes forming a gate stack on a first semiconductor region having a first conductivity type. The first semiconductor region is enclosed in a second semiconductor region having a second conductivity type different from the first conductivity type. The method further includes forming source/drain regions on opposing sides of the gate stack. The source/drain regions have the second conductivity type. The method still further includes forming a source-line contact. The source-line contact is coupled between one of the source/drain regions and the second semiconductor region.
The invention further provides methods and apparatus of varying scope.